Master simulation registry
| Simulation ID | Phase | Hypothesis | Result | Failure Mode | Status |
|---|---|---|---|---|---|
| MF-SIM-001 AND Gate | Phase I - Logic Primitives | Dual-input strand displacement produces output only under simultaneous input presence | Validated (simulation) | Leak sensitivity increases with reduced orthogonality and deeper cascades | Tier 1 reported |
| MF-SIM-002 OR Gate | Phase I - Logic Primitives | Single-input activation sufficient for output displacement | Validated (simulation) | Parallel-path density increases cooperative activation risk in deep cascades | Tier 1 reported |
| MF-SIM-003 NOT Gate | Phase I - Logic Primitives | Inversion via blocking strand displacement | Validated (simulation) | Suppression pathway dominance required to prevent spontaneous release | Tier 1 reported |
| MF-SIM-004 NAND Gate | Phase I - Logic Primitives | Complementary AND structure yields inverse output | Validated (simulation) | Orthogonality degradation increases leak susceptibility | Tier 1 reported |
| MF-SIM-005 NOR Gate | Phase I - Logic Primitives | Complementary OR structure yields inverse output | Validated (simulation) | Competing pathways require bounded rate separation | Tier 1 reported |
| MF-SIM-006 XOR Gate | Phase I - Logic Primitives | Exclusive dual-input logic achievable via multi-branch topology | Validated (simulation) | Branch complexity raises pathway interference sensitivity | Tier 1 reported |
| MF-SIM-007 Multi-input Composite Gate | Phase I - Logic Primitives | Cascaded logic preserves truth-table equivalence | Validated (simulation) | Cumulative layering increases leakage pressure | Tier 1 reported |
| MF-SIM-008 Logic Gate Chaining (AND->OR->NOT) | Phase I - Logic Primitives | Composability across cascaded gates | Validated (simulation) | Cascaded timing divergence beyond bounded depth | Tier 1 reported |
| MF-SIM-009 Dual-path Branching Logic | Phase I - Logic Primitives | Exclusive output activation across competing paths | Validated (simulation) | Branch exclusivity depends on strict orthogonality | Tier 1 reported |
| MF-SIM-010 1-bit Delay Element | Phase II - Temporal Behavior | Delay controllable via toehold modulation | Validated (simulation) | Delay windows drift when kinetic hierarchy narrows | Registry complete |
| MF-SIM-011 Toggle Latch | Phase II - Temporal Behavior | Reversible state retention achievable | Validated (simulation) | Retention weakens under increased crosstalk pressure | Registry complete |
| MF-SIM-012 Simple Flip-Flop | Phase II - Temporal Behavior | Binary persistent state switching | Validated (simulation) | Switching latency accumulates across chained states | Registry complete |
| MF-SIM-013 Hold Gate with Delay | Phase II - Temporal Behavior | Conditional hold with timed release | Validated (simulation) | Timed release becomes sensitive to diffusion bounds | Registry complete |
| MF-SIM-014 Strand Timer | Phase II - Temporal Behavior | Decay-based delay modeling | Validated (simulation) | Decay profiles diverge under thermal perturbation | Registry complete |
| MF-SIM-015 Double-buffered Gate Trigger | Phase II - Temporal Behavior | Sequential trigger gating | Validated (simulation) | Buffer overlap increases accidental early activation risk | Registry complete |
| MF-SIM-016 Conditional Delay Sequence | Phase II - Temporal Behavior | Timed conditional activation | Validated (simulation) | Conditional timing thresholds tighten under deeper sequences | Registry complete |
| MF-SIM-017 1-bit RAM Cell | Phase IIIA - Memory Architectures | Persistent rewritable memory achievable | Validated (simulation) | Memory gating introduces additional leak surfaces | Tier 1 reported |
| MF-SIM-018 2-bit RAM Array | Phase IIIA - Memory Architectures | Multi-bit memory scaling without instability | Validated (simulation) | Cross-cell interactions require tighter domain separation | Registry complete |
| MF-SIM-019 4-bit RAM Module | Phase IIIA - Memory Architectures | Addressable memory expansion | Validated (simulation) | Address complexity raises state retention sensitivity | Registry complete |
| MF-SIM-020 Enable-Gated Branch Structure | Phase IIIB - Control Logic | Conditional path activation | Validated (simulation) | Competing branch activation risk under weak gating dominance | Registry complete |
| MF-SIM-021 Multi-Path Conditional Output Network | Phase IIIB - Control Logic | Exclusive branching control | Validated (simulation) | Path exclusivity becomes fragile in dense branch topologies | Registry complete |
| MF-SIM-022 2-bit Comparator | Phase IIIC - Arithmetic Units | Binary comparison achievable via displacement cascades | Validated (simulation) | Comparator depth increases threshold sensitivity | Registry complete |
| MF-SIM-023 4-bit Ripple Carry Adder | Phase IIIC - Arithmetic Units | Carry propagation achievable sequentially | Validated (simulation) | Carry chains amplify cumulative latency | Tier 1 reported |
| MF-SIM-024 1-bit ALU Block | Phase IIIC - Arithmetic Units | Arithmetic and logical operations combinable | Validated (simulation) | Operation multiplexing increases pathway crowding | Registry complete |
| MF-SIM-025 Cascaded Multi-Gate Activation | Phase IV - Timing and Coordination | Coordinated sequential cascade without collapse | Validated (simulation) | Depth-dependent leak amplification | Registry complete |
| MF-SIM-026 Latency Stacking Analysis | Phase IV - Timing and Coordination | Cumulative delay bounded | Validated (simulation) | Timing variance accumulates with stage count | Registry complete |
| MF-SIM-027 Coordinated Multi-Stage Triggering | Phase IV - Timing and Coordination | Ordered multi-layer execution | Validated (simulation) | Trigger desynchronization risk under constrained kinetics | Registry complete |
| MF-SIM-028 External Strand-Triggered Activation | Phase V - Environmental I/O | External input drives internal logic | Validated (simulation) | Threshold misalignment under weak external signal separation | Registry complete |
| MF-SIM-029 Feedback Loop Stabilization | Phase V - Environmental I/O | Feedback stabilizes macrostate | Validated (simulation) | Feedback amplification can destabilize under high gain regimes | Registry complete |
| MF-SIM-030 Signal Amplification Cascade | Phase V - Environmental I/O | Amplified output response achievable | Validated (simulation) | Amplification chains increase leak propagation risk | Registry complete |
| MF-SIM-031 Sequential Trigger Chain | Phase VI - Instruction Sequencing | Ordered execution cascade | Validated (simulation) | Ordering drift when trigger availability windows overlap | Registry complete |
| MF-SIM-032 Conditional Branch Sequencing | Phase VI - Instruction Sequencing | Branch-dependent execution | Validated (simulation) | Conditional branch contention under tightly coupled states | Registry complete |
| MF-SIM-033 State Propagation Network | Phase VI - Instruction Sequencing | Multi-state runtime progression | Validated (simulation) | Propagation fidelity degrades with excessive state depth | Registry complete |
| MF-SIM-034 Logical AST to Strand Mapping | Phase VII - Compiler and Molebyte Formalization | Structural equivalence preserved | Validated (simulation) | Mapping inconsistency risk when graph constraints are violated | Registry complete |
| MF-SIM-035 Molebyte Instruction Encoding | Phase VII - Compiler and Molebyte Formalization | Deterministic strand architecture mapping | Validated (simulation) | Instruction encoding ambiguity under unresolved schema variants | Registry complete |
| MF-SIM-036 End-to-End Execution Chain | Phase VIII - System-Level Integration | Full layered execution stable | Validated (simulation) | Cross-layer timing drift under aggregate load | Registry complete |
| MF-SIM-037 Integrated Memory-Control-Arithmetic Stack | Phase VIII - System-Level Integration | Cross-layer stability | Validated (simulation) | Subsystem coupling increases leak and latency coupling risk | Registry complete |
| MF-SIM-038 Global Macrostate Convergence | Phase VIII - System-Level Integration | System-wide deterministic convergence | Validated (simulation) | Global convergence margin narrows near cascade depth limits | Tier 1 reported |
Registry notes
Registry values reflect structural simulation outputs and boundary observations published in the supplement corpus.
Quantitative values are not fabricated in this release. Where numerical values are required for publication-grade reporting, references use: [INSERT ACTUAL SIMULATION DATA].